Review issues — fhsim_marine_elements

Findings from code review that await an owner decision or an implementation. Each row is one file in issues/details/, which holds the evidence, the effect, the possible fix, the test that would prove it and the risk. Resolved issues are kept in issues/resolved/ so that their numbers are never reused. Issues that concern a SimObject are also shown on that model's documentation page. Audit notes that are not issues are in issues/notes.md.

How to work an item

1. Reproduce the Evidence at the file:line given in the detail file, at HEAD.
2. For a blocked item, get the owner's answer to "Decision needed" first, then set Status to ready.
3. Write the proving test, apply the fix, check the Risk paragraph.
4. git mv the file to issues/resolved/, add a | Resolved | <commit>, <date> | row, delete the matching \xrefitem reviewissue "Review issues" "Review issues" \ref fhsim_marine_elements_issue_<ID> lines from the headers, rerun the script and commit it all together.

New issue: add issues/details/<slug>.md with the metadata table but no ID row; the script assigns the next free number, writes the heading and renames the file to <TAG>-<ID>-<slug>.md.

Legend

Tag	Values
Class	BUG code does something other than its documentation or sibling code says; KNOWN-LIMITATION behaviour gap by design or omission, document rather than fix silently; ARCHITECTURE structure, dependencies, build layout, dead code and stale artefacts; DOCUMENTATION missing or wrong documentation or example; TEST test coverage or infrastructure; API public name (port, state, parameter, registration string) whose change breaks input files; SECURITY credentials and supply chain
Severity	3 wrong numbers, a crash or a secret exposure reaches a user; 2 a documented interface does not work as documented; 1 tidiness, readers and tools only
Status	blocked needs the owner decision named in the file; ready fully specified

Open issues (12)

ID	Class	Severity	Status	Models	Title
MARE-0014	BUG	3	blocked	Cable/RigidBarCable	Cable/RigidBarCable binds both ForceB<i>a and ForceB<i>b to the same slot, and reads neither
MARE-0025	BUG	3	blocked	RbCable/Cable	RbCable/Cable documents the RBCABLE_CLASSIC_INTERFACE branch, but no build defines that macro
MARE-0001	BUG	2	blocked	RbCable/Collision (class Collision; it has no documentation page because its @group line is commented out too)	RbCable/Collision is registered only in a commented-out line
MARE-0003	BUG	2	blocked	TrawlCable	TrawlCable's Heun_i branch is commented out while RundDorg's is live
MARE-0020	DOCUMENTATION	2	blocked	TrawlBeam, MooringCable, TrawlCable, RundDorg, Net/NetStructureWithConstraints	The trawl/mooring SimObjects and Net/NetStructureWithConstraints have no port or parameter documentation
MARE-0022	DOCUMENTATION	2	blocked	Net/NetStructure, Net/NetStructureArray, Net/NetStructureWakeEffect	The NetStructure family documentation tables are ??? placeholders
MARE-0004	KNOWN-LIMITATION	1	blocked	Net/NetStructure	The panel block of the NetStructure Jacobian is itself a forward difference
MARE-0005	DOCUMENTATION	1	blocked	—	Three registered classes have no documentation page
MARE-0010	KNOWN-LIMITATION	1	blocked	RbCable/RBCable, RbCable/Cable	RbCable/RBCable has no force output for end A, and the RbCable group's force-port case is unsettled
MARE-0017	ARCHITECTURE	1	blocked	RbCable/Ring	RbCable/Ring reads NumInputsPerConnector and Cm_IsAddedMassHack without using or documenting them
MARE-0018	ARCHITECTURE	1	blocked	Net/NetStructure	The OpenCL sources are never compiled
MARE-0019	ARCHITECTURE	1	blocked	—	src/net/Test/NetSolidityMeshSpec.cpp and its header are in no source list

Resolved issues (13)

ID	Class	Title	Resolved	File
MARE-0002	API	RbCable/Cable maps to class CCableRM, which kept its C prefix	9f8db23, 2026-09-16	resolved/MARE-0002-rbcable-cable-class-ccablerm-prefix.md
MARE-0006	BUG	Cable/LumpedMass reads NumElements, but the documentation and an example say numElements	d374a00, 2026-09-15	resolved/MARE-0006-cable-lumpedmass-reads-numelements.md
MARE-0007	DOCUMENTATION	Cable/LumpedMass documents an input port velWater that does not exist	d374a00, 2026-09-15	resolved/MARE-0007-cable-lumpedmass-documents-an-input-port.md
MARE-0008	ARCHITECTURE	src/cable/Cable.h carries two complete, divergent documentation blocks	d374a00, 2026-09-15	resolved/MARE-0008-src-cable-cable-h-carries-two.md
MARE-0009	DOCUMENTATION	Net/Disk documents an output port ForceB where the code registers Velocity	4a78912, 2026-09-15	resolved/MARE-0009-net-disk-documents-an-output-port.md
MARE-0011	DOCUMENTATION	Initial-condition state indices are documented as 1…N but generated 0-based	6cf95d6, 2026-09-15	resolved/MARE-0011-initial-condition-state-indices-are-documented.md
MARE-0012	BUG	Cable/Branched registers its Length<i> output port with width 3 over a scalar	3c30a67, 2026-09-15	resolved/MARE-0012-cable-branched-registers-its-length.md
MARE-0013	DOCUMENTATION	Several Cable/Branched documented names and widths do not match the code	3c30a67, 2026-09-15	resolved/MARE-0013-several-cable-branched-documented-names.md
MARE-0015	DOCUMENTATION	Cable/RigidBarCable documents PosR/VelR as 1-based and misspells its own parameter	e14a2bb, 2026-09-15	resolved/MARE-0015-cable-rigidbarcable-documents-posr-velr.md
MARE-0016	BUG	RbCable/Ring computes a modulus by NumConnectors before checking it is non-zero	a7f8874, 2026-09-15	resolved/MARE-0016-rbcable-ring-computes-a-modulus.md
MARE-0021	ARCHITECTURE	Three dead if (false /* v3: IntegratorEngine check removed */) blocks	9f8db23, 2026-09-16	resolved/MARE-0021-dead-integratorengine-if-false-blocks.md
MARE-0023	API	BouyancyFactor is misspelled, and the misspelling is load-bearing	9f8db23, 2026-09-16	resolved/MARE-0023-bouyancyfactor-misspelling-load-bearing.md
MARE-0024	ARCHITECTURE	Dead sources and dead references in the tree	9f8db23, 2026-09-16	resolved/MARE-0024-dead-sources-and-references.md